The present invention relates to integrated circuits and their fabrication. More specifically, the invention relates to the structure and fabrication of a via contact to a diffusion region at a top surface of a single-crystal semiconductor region of a substrate.
A particular challenge encountered in the fabrication of integrated circuits is the formation of metallic via contacts to diffusion regions (referred to alternatively as “diffusions”) of semiconductor devices. Such diffusion regions are formed in single-crystal semiconductor regions of a substrate, such that an ohmic contact is made between the metallic material in the via and the semiconductor material of the diffusion region. The challenge is particularly difficult to provide a robust structure and method of forming metallic via contacts having acceptably low contact resistance between the metal and the diffusion region, over all chip locations of an entire wafer.
Thus, processes and structures known heretofore have resulted in acceptable contact resistance, but only when a sufficiently thick layer of a metal silicide, e.g., greater than 20-25 nm of cobalt silicide (CoSi2) or nickel monosilicide (NiSi), for example, is provided at a top surface of the diffusion region. In one such exemplary process, a metal silicide layer is formed in contact with the diffusion region of the substrate, after which an interlevel dielectric (ILD) is formed, typically consisting essentially of a highly flowable, planarizing dielectric such as borophosphosilicate glass (BPSG), undoped silicate glass (USG) or silicon dioxide deposited from a tetraethylorthosilicate (TEOS) precursor.
Thereafter, the ILD is patterned to form an opening over the metal suicide layer. A sputter clean process is then performed to clean the surface of the pre-existing metal silicide layer to make it ready for the deposition of metallic layers which enhance the conductive contact and to prepare the via to be filled with tungsten by a chemical vapor deposition (CVD) technique. However, the sputter clean process consumes some of the pre-existing metal silicide layer at the top surface of the single-crystal semiconductor region. In an example, the sputter clean process removes about 8 nm of the metal silicide. Thereafter, a thin layer of a metal such as titanium (Ti) is sputter deposited inside the via opening. For example, a layer of titanium having a thickness of 20 angstroms (Å) or less is deposited at the bottom of the opening, the deposited titanium being, illustratively, about 100 Å thick where it overlies the ILD in the field. The Ti layer promotes adhesion to the bottom and sidewalls of the opening. The Ti layer is also used to getter oxygen from a native oxide that forms on the surface of the pre-existing metal silicide layer. The Ti layer used in the conventional process is deposited to a thickness of 20 Å or less because such thickness is sufficient to promote desired adhesion properties and to perform oxygen gettering from the underlying metal silicide layer.
Thereafter, a diffusion barrier layer such as titanium nitride (TiN) is CVD deposited onto the underlying Ti layer, as a barrier to the diffusion and electromigration of material to and from the underlying Ti and silicide layers and materials present during subsequent depositions. Thereafter, a metal such as W (tungsten) is deposited, such as by CVD from a tungsten hexaflouride (WF6) precursor, to fill the via after forming the Ti and TiN layers.
In the conventional process, a Ti layer having a thickness greater than 20 Å is undesirable because the sputter deposition of titanium takes up significant time, impacting the throughput and cost of each wafer. In addition, a thicker Ti layer is undesirable because the sputtering process tends to deposit more Ti at the entrance (top) surface of a via, while depositing comparatively less Ti at the bottom of the via. Accordingly, a byproduct of the Ti sputter deposition is a more constricted opening, sometimes having a re-entrant profile, that is more difficult to fill in subsequent depositions to form the TiN diffusion barrier layer and the W metal fill. If the Ti layer is not kept to the minimum thickness, the W fill metal deposition must be more tightly controlled to prevent voids and pinch-off of the via opening from occurring during deposition. Still another reason limiting the thickness of the Ti layer is a goal of the conventional process to intentionally limit the amount of Ti present in the via. The conventional process intentionally limits the amount of Ti in the via as a way of limiting damage, in case the TiN diffusion barrier layer fails in some areas of the wafer during tungsten CVD. If the TiN layer fails as a barrier, this allows the Ti to interact with the WF6 precursor gas. However, WF6 produces volatile compounds when it comes into contact with portions of the Ti layer. Such volatile compounds destructively impact the prior deposited layers, the W layer during deposition and subsequently deposited layers, causing severe degradation of the via structure and degrading its performance. Thus, in the conventional process, the Ti layer is kept intentionally thin for a variety of reasons, all of which are intended to improve the quality of the contact structure.
However, the above-described process only produces acceptable results when the pre-existing silicide layer underlying the ILD, i.e., the CoSi2 or NiSi layer, is relatively thick, i.e., having a thickness in excess of 20 nm to 25 nm. That thickness is needed in order for the silicide layer under the ILD to remain to a sufficient thickness at locations all over the wafer after the openings in the ILD are subjected to the above-described sputter clean process. If a smaller thickness of the silicide were used, e.g., having a nominal thickness of 10 to 12 nm, the sputter clean process could result in removing the silicide layer entirely in some locations of the wafer. In such case, poor contact to the diffusion region of the semiconductor material would result, having poor contact resistance. This is a problem that needs to be addressed.